IOMD2

The IOMD is the central controller for the whole computer.
An idea of its complexity can be given by the functions it performs:
- SDRAM & VRAM Control
- StrongARM and Multiprocessing Control
- Multiprocessor Communications and Semaphore Lists
- Video Control
- Address Decode
- Interrupt Control
- Timers
- I/O Cycle Control
- ROM Control
- I/O DMA Control
The IOMD2 provides SDRAM support for the processor, as the current SA-110 is unable to interface directly with this type of memory.
It also provides multiprocessing support, in anticipation of multiple-ARM processor cards. It has been suggested that the Phoebe approach is based on methods used in the Hydra project.
ARM processors will not be easy to multiprocess - they are not designed for it. Synchronising the first level caches of several ARMs is a problem, as there is no method of snooping on their contents.
IOMD2 implements an area of Static RAM, organised as a series of circular lists. This operates a little like a second level cache, whilst also allowing the coherence of the caches to be checked.
Acorn is planning to look at multiprocessor cards for Phoebe following the initial launch.

The IOMD2 has been designed in-house by Acorn.
The original IOMD was specified by Acorn, but designed by ARM. This time, Acorn trained a group of their Hardware Engineers in IC design and VLSI Hardware Description Language (VHDL), and set them to work to produce the new design.
As a result, the Phoebe prototypes have an IOMD2 implemented on a Field-Programmable Gate Array (FPGA), an easily-programmed digital IC which is often used in prototyping.
Production Phoebes will not have the FPGA; IOMD2 will be implemented in a custom IC by that time. This will further improve the machine's performance, as FPGAs are, by their nature, not as fast as dedicated ICs.

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