VIDC20+ Video Controller

Updated 31st May.

VIDC20+, also known as VIDC20 revision R, is the latest iteration of the design used in the RiscPC.
It has been redesigned for a 0.6�m feature size, compared to the original device's 1.1�m feature size.
Shrinking the IC allows it to operate at higher speeds: the pixel clock is now 200MHz, compared to the RiscPC's 100MHz.
The VIDC20+ is provided with 4Mbytes of dual-port EDO VRAM, soldered to the motherboard.
This combination is expected to achieve resolutions of 1280 x 1024 at 75Hz refresh in 32,000 colours. It may be possible to achieve 1600 x 1200 in 32,000 colours, or 1280 x 1024 in 16 million colours.
The redesign for 0.6�m was carried out by Cirrus Logic, as part of the ARM7500FE development. A cut-down version of the VIDC20, the VIDC2L, was produced for the integrated processor; the revision R was a by-product of that work.

It has been pointed out that a resolution of 1280 by 1024 in 16 million colours exceeds the 4Mbytes of available VRAM, assuming that each pixel uses 32 bits of storage.
Acorn's Dave Walker would not confirm whether this was a mistake. He raised the possibility that Phoebe may actually use 24 bits per pixel, converting between 32 and 24 bits on the fly.

Thanks to Paul Shuck and Dave Walker for this information.