Phoebe 2100: Main Memory
Wakefield '98
- Phoebe has been provided with two 172 pin Dual in-line Memory Module (DIMM) sockets.
- These are intended to take Synchronous DRAM (SDRAM); the system is likely to be supplied with one 32Mbyte module.
- Despite SDRAMs being essentially 64 bit wide devices, the data bus is 32 bits wide. In the current ARM range, only the SA-1500 has a 64 bit data bus.
- The SDRAM interface is provided by the IOMD2, as the SA-110 does not have the necessary control circuitry itself.
- With two sockets, the theoretical memory limit is 512Mbytes. However, there are currently no 256Mbyte DIMMS on the market, so the practical limit is 256Mbytes using two 128Mbyte devices.
- Synchronous DRAM is clocked like the processor, allowing faster sequential data transfers. For example, a sequential write to a Fast page mode DRAM (FPDRAM) - as used in the RiscPC - would take 5 clock cycles. The same write to a SDRAM would take 2 clock cycles.
- The processor bus speed in Phoebe has been increased to 64MHz, from 16MHz in the old machines.
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